碼表，顯示分與秒VHDL20240608_clock_mmss
碼表，顯示分與秒VHDL20240608_clock_mmss
https://youtube.com/shorts/CG_sV1ZLDdM
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity VHDL20240608_clock_mmss is
port
(
clk_4M:in std_logic;
rst:in std_logic;
clk_555:in std_logic;
seg7_out:out std_logic_vector(6 downto 0);
seg7_scan:out std_logic_vector(3 downto 0);
BCD:out std_logic_vector(3 downto 0);
seg7_sec:out std_logic
);
end VHDL20240608_clock_mmss;
architecture aa of VHDL20240608_clock_mmss is
signal cnt1:integer range 0 to 1999:=0;
signal clk_2k:std_logic:='0';
signal clk_D5:std_logic:='0';
signal cnt2:std_logic_vector(1 downto 0):="00";
signal m1,m0,s1,s0:std_logic_vector(3 downto 0):="0000";
signal seg7_reg:std_logic_vector(3 downto 0):="0000";
begin
process(clk_4M)
begin
if rising_edge(clk_4M) then
if cnt1=1999 then
cnt1<=0;
clk_2k<=not clk_2k;
else
cnt1<=cnt1+1;
end if;
end if;
end process;
process(clk_2k)
begin
if rising_edge(clk_2k) then
clk_D5<=clk_555;
cnt2<=cnt2+1;
end if;
end process;
process(clk_D5,rst)
begin
if rst='0' then
m1<="0000";
m0<="0000";
s1<="0000";
s0<="0000";
elsif rising_edge(clk_D5) then
if s0="1001" then
s0<="0000";
if s1="0101" then
s1<="0000";
if m0="1001" then
m0<="0000";
if m1<="0101" then
m1<="0000";
else
m1<=m1+1;
end if;
else
m0<=m0+1;
end if;
else
s1<=s1+1;
end if;
else
s0<=s0+1;
end if;
end if;
end process;
process(cnt2)
begin
case cnt2 is
when "00" =>
seg7_reg<=s0;
seg7_scan<="1110";
when "01" =>
seg7_reg<=s1;
seg7_scan<="1101";
when "10" =>
seg7_reg<=m0;
seg7_scan<="1011";
when "11" =>
seg7_reg<=m1;
seg7_scan<="0111";
end case;
end process;
seg7_out<= "1000000" when seg7_reg="0000" else
"1111001" when seg7_reg="0001" else
"0100100" when seg7_reg="0010" else
"0110000" when seg7_reg="0011" else
"0011001" when seg7_reg="0100" else
"0010010" when seg7_reg="0101" else
"0000010" when seg7_reg="0110" else
"1111000" when seg7_reg="0111" else
"0000000" when seg7_reg="1000" else
"0011000" when seg7_reg="1001" else
"1111111";
seg7_sec<=not clk_555;
BCD<=s0;
end aa;
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