4位元計數器0000to9999 VHDL20240608_0000to9999

 4位元計數器0000to9999 VHDL20240608_0000to9999

https://youtube.com/shorts/GxH4fG-qXik





library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

entity VHDL20240608_0000to9999 is

port

(

clk_4M:in std_logic;

rst:in std_logic;

clk_555:in std_logic;

seg7_out:out std_logic_vector(6 downto 0);

seg7_scan:out std_logic_vector(3 downto 0);

seg7_sec:out std_logic:='1'

);

end VHDL20240608_0000to9999;

architecture aa of VHDL20240608_0000to9999 is

signal cnt1:integer range 0 to 1999:=0;

signal clk_2k:std_logic:='0';

signal cnt2:std_logic_vector(1 downto 0):="00";

signal clk_555_2:std_logic:='0';

signal v0,v1,v2,v3:std_logic_vector(3 downto 0):="0000";

signal seg7_reg:std_logic_vector(3 downto 0):="0000";

begin

process(clk_4M,rst)

begin

if rising_edge(clk_4M) then

if cnt1=1999 then

cnt1<=0;

clk_2k<=not clk_2k;

else

cnt1<=cnt1+1;

end if;

end if;

end process;

process(clk_2k)

begin

if rising_edge(clk_2k) then

cnt2<=cnt2+1;

clk_555_2<=clk_555;

end if;

end process;

process(clk_555_2, rst)

begin

if rst='0' then

v0<="0000";

v1<="0000";

v2<="0000";

v3<="0000";

elsif rising_edge(clk_555_2)then

if v0="1001" then

v0<="0000";

if v1="1001" then

v1<="0000";

if v2="1001" then

v2<="0000";

if v3="1001" then

v3<="0000";

else

v3<=v3+1;

end if;

else

v2<=v2+1;

end if;

else

v1<=v1+1;

end if;

else

v0<=v0+1;

end if;

end if;

end process;

process(cnt2)

begin

case cnt2 is

when "00"=>

seg7_reg<=v0;

seg7_scan<="1110";

when "01"=>

seg7_reg<=v1;

seg7_scan<="1101";

when "10"=>

seg7_reg<=v2;

seg7_scan<="1011";

when "11"=>

seg7_reg<=v3;

seg7_scan<="0111";

end case;

end process;

seg7_out<= "1000000" when seg7_reg="0000"else

"1111001" when seg7_reg="0001"else

"0100100" when seg7_reg="0010"else

"0110000" when seg7_reg="0011"else

"0011001" when seg7_reg="0100"else

"0010010" when seg7_reg="0101"else

"0000010" when seg7_reg="0110"else

"1111000" when seg7_reg="0111"else

"0000000" when seg7_reg="1000"else

"0011000" when seg7_reg="1001"else

"1111111";

end aa;

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