數位電子乙級第2題腳位E顯示M CPLD 20240606

 數位電子乙級第2題腳位E顯示M CPLD 20240606

VHDL_20240606_DE2_E_M

https://youtube.com/shorts/Ykl7OLIymv0

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

entity VHDL_20240606_DE2_E_M is

port(

clk_4M:in std_logic;

key_col:in std_logic_vector(2 downto 0);

key_row:buffer std_logic_vector(3 downto 0);

seg7_out:out std_logic_vector(6 downto 0));

end VHDL_20240606_DE2_E_M;

architecture aa of VHDL_20240606_DE2_E_M is

signal cnt1:integer range 0 to 1999:=0;

signal clk_2k:std_logic:='0';

signal cnt2:std_logic_vector(1 downto 0):="00";

signal temp:std_logic_vector(6 downto 0):="1111111";

signal cnt3:std_logic_vector(6 downto 0):="0000000";

begin

process(clk_4M)

begin

if rising_edge(clk_4M) then

if cnt1=1999 then

cnt1<=0;

clk_2k<=not clk_2k;

else

cnt1<=cnt1+1;

end if;

end if;

end process;

process(clk_2k,key_col)

begin

if rising_edge(clk_2k)then

if key_col="111" then

cnt3<="0000000";

cnt2<=cnt2+1;

elsif cnt3="1111111" then

cnt3<="0000000";

temp(3 downto 0)<=key_row(3 downto 0);

temp(6 downto 4)<=key_col(2 downto 0);

else

cnt3<=cnt3+1;

end if;

end if;

end process;

key_row<= "1110"when(cnt2=0)else

"1101"when(cnt2=1)else

"1011"when(cnt2=2)else

"0111";

seg7_out<= "1111001" when(temp="0110111")else

"0100100" when(temp="1010111")else

"0110000" when(temp="1100111")else

"0011001" when(temp="0111011")else

"0010010" when(temp="1011011")else

"0000010" when(temp="1101011")else

"1111000" when(temp="0111101")else

"0000000" when(temp="1011101")else

"0011000" when(temp="1101101")else

"1011100" when(temp="0111110")else

"1000000" when(temp="1011110")else

"1100011" when(temp="1101110")else

"1111111";

end aa;