數位電子乙級第1題CPLD VHDL_20240608_DE1 顯示POSE.

 數位電子乙級第1題CPLD VHDL_20240608_DE1 顯示POSE.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

entity VHDL_20240608_DE1 is

port(

clk_4M:in std_logic;

seg7_out:out std_logic_vector(7 downto 0);

seg7_scan:out std_logic_vector(3 downto 0));

end VHDL_20240608_DE1;

architecture aa of VHDL_20240608_DE1 is

signal cnt1:integer range 0 to 1999:=0;

signal cnt2:std_logic_vector(1 downto 0):="00";

signal seg7_v3:std_logic_vector(7 downto 0):="01110011";--P

signal seg7_v2:std_logic_vector(7 downto 0):="00111111";--O

signal seg7_v1:std_logic_vector(7 downto 0):="01101101";--S

signal seg7_v0:std_logic_vector(7 downto 0):="11111001";--E.

begin

process(clk_4M)

begin

if rising_edge(clk_4M) then

if cnt1=1999 then

cnt1<=0;

cnt2<=cnt2+1;

else

cnt1<=cnt1+1;

end if;

end if;

end process;

seg7_scan<= "0001"when(cnt2=0)else

"0010"when(cnt2=1)else

"0100"when(cnt2=2)else

"1000";

seg7_out<= seg7_v0 when(cnt2=0)else

seg7_v1 when(cnt2=1)else

seg7_v2 when(cnt2=2)else

seg7_v3;

end aa;