VHDL20240527_counter_fsm 有限狀態計數器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity VHDL20240527_counter_fsm is
port(
clk_4M:in std_logic;
reset:in std_logic;
start:in std_logic;
seg7_scan:out std_logic_vector(3 downto 0):="1110";
state_BCD:out std_logic_vector(2 downto 0):="000";
seg7_out:out std_logic_vector(6 downto 0));
end VHDL20240527_counter_fsm;
architecture aa of VHDL20240527_counter_fsm is
signal cnt1:integer range 0 to 1999:=0;
signal cnt2:integer range 0 to 1999:=0;
signal clk_2k:std_logic:='0';
signal clk_sec:std_logic:='0';
type state_type is (IDLE, COUNTING, DONE);
signal state:state_type:=IDLE;
signal counter:std_logic_vector(3 downto 0):="0000";
begin
process(clk_4M)
begin
if rising_edge(clk_4M) then
cnt1<=cnt1+1;
if cnt1=1999 then
cnt1<=0;
clk_2k<=not clk_2k;
end if;
end if;
end process;
process(clk_2k)
begin
if rising_edge(clk_2k) then
cnt2<=cnt2+1;
if cnt2=499 then
cnt2<=0;
clk_sec<=not clk_sec;
end if;
end if;
end process;
process(clk_sec, reset)
begin
if reset='0' then
state<=IDLE;
counter<="0000";
state_BCD<="100";
elsif start='0' then
state<=COUNTING;
state_BCD<="010";
elsif rising_edge(clk_sec) then
case state is
when IDLE =>
null;
when COUNTING =>
if counter="1001" then
state<=DONE;
state_BCD<="001";
else
counter<=counter+1;
end if;
when DONE =>
null;
end case;
end if;
end process;
seg7_out<= "1000000" when(counter=0)else
"1111001" when(counter=1)else
"0100100" when(counter=2)else
"0110000" when(counter=3)else
"0011001" when(counter=4)else
"0010010" when(counter=5)else
"0000010" when(counter=6)else
"1111000" when(counter=7)else
"0000000" when(counter=8)else
"0011000" when(counter=9)else
"1111111";
end aa;
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