VHDL20240517_seg7_ooxx_AEEE

 VHDL20240517_seg7_ooxx_AEEE

show OOXX on AEEE board 謝謝亞東電子系

腳位

37 a

33 b

27 c

29 d

28 e

34 f

8 g

31 dp

9 d1 v3 千

11 d2 v2 百

12 d3 v1 十

14 d4 v0 個

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity VHDL20240517_seg7_ooxx_AEEE is

port(

clk_4M:in std_logic;

seg7_high:out std_logic_vector(7 downto 0);

seg7_scan:out std_logic_vector(3 downto 0));

end VHDL20240517_seg7_ooxx_AEEE;

architecture aa of VHDL20240517_seg7_ooxx_AEEE is

signal cnt1:integer range 0 to 1999:=0;

signal clk_2k:std_logic:='0';

signal cnt2:std_logic_vector(1 downto 0);

signal seg7_v3:std_logic_vector(7 downto 0):="00111111";--O

signal seg7_v2:std_logic_vector(7 downto 0):="00111111";--O

signal seg7_v1:std_logic_vector(7 downto 0):="01110110";--X

signal seg7_v0:std_logic_vector(7 downto 0):="01110110";--X

begin

process(clk_4M)

begin

if rising_edge(clk_4M) then

cnt1<=cnt1+1;

if cnt1=1999 then

cnt1<=0;

clk_2k<=not clk_2k;

end if;

end if;

end process;

process(clk_2k)

begin

if rising_edge(clk_2k) then

cnt2<=cnt2+1;

end if;

end process;

seg7_scan<= "0001"when(cnt2=0)else

"0010"when(cnt2=1)else

"0100"when(cnt2=2)else

"1000"when(cnt2=3);

seg7_high<= seg7_v3 when(cnt2=3)else

seg7_v2 when(cnt2=2)else

seg7_v1 when(cnt2=1)else

seg7_v0 when(cnt2=0);

end aa;