VHDL20240517_seg7_OOXX

 

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity VHDL20240517_seg7_ooxx is

port(

clk_4M:in std_logic;

seg7_sec_low:out std_logic:='1';

seg7_v3v2v1v0_low:out std_logic_vector(3 downto 0);

seg7_gfedcba_low:out std_logic_vector(6 downto 0));

end VHDL20240517_seg7_ooxx;

architecture aa of VHDL20240517_seg7_ooxx is

signal cnt_1:integer range 0 to 1999:=0;

signal cnt_2:std_logic_vector(1 downto 0):="00";

signal clk_2k:std_logic:='0';

signal seg7_gfedcba:std_logic_vector(6 downto 0);

signal seg7_v3_gfedcba:std_logic_vector(6 downto 0):="0111111";--O

signal seg7_v2_gfedcba:std_logic_vector(6 downto 0):="0111111";--O

signal seg7_v1_gfedcba:std_logic_vector(6 downto 0):="1110110";--X

signal seg7_v0_gfedcba:std_logic_vector(6 downto 0):="1110110";--X

signal seg7_v3v2v1v0:std_logic_vector(3 downto 0);

begin

process(clk_4M)

begin

if rising_edge(clk_4M) then

cnt_1<=cnt_1+1;

if cnt_1=1999 then

cnt_1<=0;

clk_2k<=not clk_2k;

end if;

end if;

end process;

process(clk_2k)

begin

if rising_edge(clk_2k) then

cnt_2<=cnt_2+1;

end if;

end process;

seg7_v3v2v1v0<= "0001"when(cnt_2=0)else

"0010"when(cnt_2=1)else

"0100"when(cnt_2=2)else

"1000"when(cnt_2=3);

seg7_gfedcba<= seg7_v3_gfedcba when(cnt_2=3)else

seg7_v2_gfedcba when(cnt_2=2)else

seg7_v1_gfedcba when(cnt_2=1)else

seg7_v0_gfedcba when(cnt_2=0);

seg7_v3v2v1v0_low<= not seg7_v3v2v1v0;

seg7_gfedcba_low<= not seg7_gfedcba;

 end aa;