VHDL20240517_keyshow_a
VHDL20240517_keyshow_a
感謝亞東電子系
https://youtube.com/shorts/BHhfNuC_SLg?si=OPEHQ5l7O17x3C_M
num c2 c1 c0 r3 r2 r1 r0 g f e d c b a
1 0 1 1 0 1 1 1 1 1 1 1 0 0 1
2 1 0 1 0 1 1 1 0 1 0 0 1 0 0
3 1 1 0 0 1 1 1 0 1 1 0 0 0 0
4 0 1 1 1 0 1 1 0 0 1 1 0 0 1
5 1 0 1 1 0 1 1 0 0 1 0 0 1 0
6 1 1 0 1 0 1 1 0 0 0 0 0 1 0
7 0 1 1 1 1 0 1 1 1 1 1 0 0 0
8 1 0 1 1 1 0 1 0 0 0 0 0 0 0
9 1 1 0 1 1 0 1 0 0 1 1 0 0 0
s 0 1 1 1 1 1 0 0 1 0 0 1 1 1
0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 下[
t 1 1 0 1 1 1 0 0 1 1 0 0 1 1 下]
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity VHDL20240517_keyshow_a is
port(
clk_4M:in std_logic;
key_c:in std_logic_vector(2 downto 0);
key_r:buffer std_logic_vector(3 downto 0);
seg7_out:out std_logic_vector(6 downto 0));
end VHDL20240517_keyshow_a;
architecture aa of VHDL20240517_keyshow_a is
signal cnt1:integer range 0 to 1999:=0;
signal cnt2:std_logic_vector(1 downto 0):="00";
signal cnt3:integer range 0 to 99:=0;
signal clk_2k:std_logic:='0';
signal trig:std_logic:='1';
signal key_num:std_logic_vector(6 downto 0);
signal seg7_reg:std_logic_vector(6 downto 0);
begin
process(clk_4M)
begin
if rising_edge(clk_4M) then
cnt1<=cnt1+1;
if cnt1=1999 then
cnt1<=0;
clk_2k<= not clk_2k;
end if;
end if;
end process;
process(clk_2k,trig)
begin
if rising_edge(clk_2k) then
if trig/='1' then
cnt2<=cnt2+1;
end if;
end if;
end process;
process(key_c)
begin
if key_c /="111" then
trig<='1';
else
trig<='0';
end if;
end process;
key_r<= "1110" when(cnt2=0)else
"1101" when(cnt2=1)else
"1011" when(cnt2=2)else
"0111" when(cnt2=3);
key_num(3 downto 0)<=key_r(3 downto 0);
key_num(6 downto 4)<=key_c(2 downto 0);
seg7_reg<= "1111001" when(key_num="0110111")else
"0100100" when(key_num="1010111")else
"0110000" when(key_num="1100111")else
"0011001" when(key_num="0111011")else
"0010010" when(key_num="1011011")else
"0000010" when(key_num="1101011")else
"1111000" when(key_num="0111101")else
"0000000" when(key_num="1011101")else
"0011000" when(key_num="1101101")else
"0100111" when(key_num="0111110")else
"1000000" when(key_num="1011110")else
"0110011" when(key_num="1101110")else
"1111111";
process(clk_2k)
begin
if rising_edge(clk_2k) then
if trig='1' then
cnt3<=cnt3+1;
if cnt3=99 then
cnt3<=0;
seg7_out<=seg7_reg;
end if;
else
cnt3<=0;
end if;
end if;
end process;
end aa;
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