mytsaii，老蔡的教學網頁

https://youtube.com/shorts/xX-JP7SjK-I?si=XezkWrq6dcKhDNTT  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity VHDL20240527_counter_fsm is port( clk_4M:in std_logic; reset:in std_logic; start:in std_logic; seg7_scan:out std_logic_vector(3 downto 0):="1110"; state_BCD:out std_logic_vector(2 downto 0):="000"; seg7_out:out std_logic_vector(6 downto 0)); end VHDL20240527_counter_fsm; architecture aa of VHDL20240527_counter_fsm is signal cnt1:integer range 0 to 1999:=0; signal cnt2:integer range 0 to 1999:=0; signal clk_2k:std_logic:='0'; signal clk_sec:std_logic:='0'; type state_type is (IDLE, COUNTING, DONE); signal state:state_type:=IDLE; signal counter:std_logic_vector(3 downto 0):="0000"; begin process(clk_4M) begin if rising_edge(clk_4M) then cnt1<=cnt1+1; if cnt1=1999 then cnt1<=0; clk_2k<=not

數位電子乙級第1題腳位E顯示M 20240522 https://youtu.be/qaVNEgb1fi0 打chrome 搜尋測試參考資料 進入勞動部網站gov.tw 搜尋數位電子 下載術科題本PDF 位置放桌面(老師是SD卡)，學號(老師是class1110XX)，建立新資料夾DE1_20240522 進入DE1_20240522資料夾 儲存PDF檔 下載library及燒錄檔 位置就預設(剛剛的位置) 進入剛剛的資料夾 對著7z按右鍵解壓縮至此 再對著kicad_library(2).zip按右鍵解壓縮至此 再對著燒錄檔.7z按右鍵解壓縮至此 打開題本117002B11.pdf 腳位E 顯示M 術科測試編號後3碼(學號後3碼) 試題編號1 舉例，廖東濬學號111033 廖東濬顯示033.1 汪軒承就是014.1 張泳儕就是015.1 林威廷就是004.1 劉華恩就是008.1 陳禹全就是003.1 老師就是0XX.1 kicad資料夾是崗位號碼(座號)_LAYOUT 假設老師的座號78 老師的資料夾就要設 78_LAYOUT 78_CPLD 四位數顯示裝置 腳位E 顯示M 老師要顯示0XX.1 打開kicad 關掉舊專案 file, close project 建立新專案 file, new project 專案的位置 桌面(老師是SD卡)，學號(老師是class1110XX)，DE1_20240522，78_LAYOUT 檔名DE1_20240522 save kicad_library 進入kicad_library New_Library.kicad_sym檔案改成New_Library20240522.kicad_sym New_Library.pretty資料夾改成 New_Library20240522.pretty 回到kicad symbol editor(元件編輯器) 新增資料庫 file, add library global ok 位置 桌面(老師是SD卡)，學號(老師是class1110XX)，DE1_20240522，kicad_library New_Library20240522.kicad_sym 就會得到資料庫匯入 資料庫置頂 改資料庫內的元件 3x4keypad 第二題，暫時不用 4_digits_7seg_cc 要改腳位

 VHDL20240517_keyshow_a 感謝亞東電子系 https://youtube.com/shorts/BHhfNuC_SLg?si=OPEHQ5l7O17x3C_M num c2 c1 c0 r3 r2 r1 r0 g f e d c b a 1 0 1 1 0 1 1 1 1 1 1 1 0 0 1 2 1 0 1 0 1 1 1 0 1 0 0 1 0 0 3 1 1 0 0 1 1 1 0 1 1 0 0 0 0 4 0 1 1 1 0 1 1 0 0 1 1 0 0 1 5 1 0 1 1 0 1 1 0 0 1 0 0 1 0 6 1 1 0 1 0 1 1 0 0 0 0 0 1 0 7 0 1 1 1 1 0 1 1 1 1 1 0 0 0 8 1 0 1 1 1 0 1 0 0 0 0 0 0 0 9 1 1 0 1 1 0 1 0 0 1 1 0 0 0 s 0 1 1 1 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 下[ t 1 1 0 1 1 1 0 0 1 1 0 0 1 1 下] 8 c0 c2 9 c1 c1 11 c2 c0 12 r0 r3 14 r1 r2 16 r2 r1 18 r3 r0

 VHDL20240517_seg7_ooxx_AEEE show OOXX on AEEE board 謝謝亞東電子系 腳位 37 a 33 b 27 c 29 d 28 e 34 f 8 g 31 dp 9 d1 v3 千 11 d2 v2 百 12 d3 v1 十 14 d4 v0 個 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity VHDL20240517_seg7_ooxx_AEEE is port( clk_4M:in std_logic; seg7_high:out std_logic_vector(7 downto 0); seg7_scan:out std_logic_vector(3 downto 0)); end VHDL20240517_seg7_ooxx_AEEE; architecture aa of VHDL20240517_seg7_ooxx_AEEE is signal cnt1:integer range 0 to 1999:=0; signal clk_2k:std_logic:='0'; signal cnt2:std_logic_vector(1 downto 0); signal seg7_v3:std_logic_vector(7 downto 0):="00111111";--O signal seg7_v2:std_logic_vector(7 downto 0):="00111111";--O signal seg7_v1:std_logic_vector(7 downto 0):="01110110";--X signal seg7_v0:std_logic_vector(7 downto 0):="01110110";--X begin process(clk_4M)

  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity VHDL20240517_seg7_ooxx is port( clk_4M:in std_logic; seg7_sec_low:out std_logic:='1'; seg7_v3v2v1v0_low:out std_logic_vector(3 downto 0); seg7_gfedcba_low:out std_logic_vector(6 downto 0)); end VHDL20240517_seg7_ooxx; architecture aa of VHDL20240517_seg7_ooxx is signal cnt_1:integer range 0 to 1999:=0; signal cnt_2:std_logic_vector(1 downto 0):="00"; signal clk_2k:std_logic:='0'; signal seg7_gfedcba:std_logic_vector(6 downto 0); signal seg7_v3_gfedcba:std_logic_vector(6 downto 0):="0111111";--O signal seg7_v2_gfedcba:std_logic_vector(6 downto 0):="0111111";--O signal seg7_v1_gfedcba:std_logic_vector(6 downto 0):="1110110";--X signal seg7_v0_gfedcba:std_logic_vector(6 downto 0):="1110110";--X signal seg7_v3v2v1v0:std_logic_vector(3 downto 0); begin process(clk_4M) begin if ris